Time Duration Speaker & Affiliation Talk Details
9:30 AM 15 Mins Welcome and Inaugural Address
9:45 AM 45 Mins Dr. Harald Gossner, Senior Principal Engineer, Intel, Germany ESD Targets and Testing methods for D2D Interfaces (Keynote)
10:30 AM 30 Mins Prof. David Pommerenke, Graz University of Technology Measurement of currents and fields of CDM discharges with > 20 GHz bandwidth (Invited*)
11:00 AM 30 Mins Break
11:30 AM 30 Mins Dr. Sergej Bub, Principal System Level ESD Expert, Nexperia Germany GmbH, Germany ESD Protection and ESD Simulation for Automotive Interfaces (Invited)
12:00 PM 30 Mins Dr. Dolphin Abessolo Bidzo, Senior Principal RF, High-Speed ESD & Latch-Up Design Engineer, NXP Semiconductors, Netherlands ESD Robustness Challenges for RF and High-Speed I/O Applications (Invited*)
12:30 PM 30 Mins Prof. Susanna Reggiani, Full Professor, University of Bologna, Italy TCAD-based physical modeling of SCR-LDMOS improving ESD protection with high holding voltages (Invited)
1:00 PM 90 Mins Networking Lunch
2:30 PM 30 Mins Mr. Leonardo Di Biccari, ESD protection development manager, STMicroelectronics, Italy Charge trapping mechanism in thick oxide of HV LDMOS under CDM events (Invited*)
3:00 PM 20 Mins Shravya N Raj, Indian Institute of Science Why Schottky Contact in LDMOS Protects It From Filament-Driven Catastrophic ESD Failure? (Ph.D. Talk)
3:20 PM 20 Mins Mayank Yadav, Indian Institute of Science Junction Engineered FinFET SCR for Ultimate Tunability of Trigger and Holding Voltage (Ph.D. Talk)
3:40 PM 20 Mins Harihar Nath, Indian Institute of Science Physics Based Modeling of Space Charge Modulation Snapback Phenomenon in the TLP Characteristics of HV LDMOS Devices (Ph.D. Talk)
4:00 PM 20 Mins Mitesh Goyal, Indian Institute of Science Engineering SCR for better transient characteristics and for high area efficiency (Ph.D. Talk)
4:20 PM 25 Mins Coffee Break
4:45 PM 60 Mins TBD Panel Session (TBD)
5:45 PM 90 Mins Poster Session
7:15 PM 120 Mins Chair's Reception & Dinner

* In online mode

Time Duration Speaker & Affiliation Talk Details
9:00 AM 45 Mins Christopher Almeras, Sr. Principal Engineer, ESD Technologist, Raytheon, United States Optimizing the Effectiveness of an ESD Control Program Through Enhanced Training (Keynote*)
9:45 AM 45 Mins Dr. Charvaka Duvvury, IEEE Fellow, iT2 Technologies Celebrating 20 Years of Influencing ESD Targets, Standards, and Test Methods (Keynote)
10:30 AM 30 Mins Dr. Mirko Scholz, Principal Engineer, Infineon Technologies AG, Germany The ESDA Technology Roadmap (Invited)
11:00 AM 30 Mins Break
11:30 AM 30 Mins Prof. Isabella Rossetto, Associate Professor, University of Padova - Department of Information Engineering, Italy Investigation of ESD effects on normally-off p-GaN gate power HEMTs by TLP analysis and numerical simulation (Invited)
12:00 PM 30 Mins Dr. Matteo Buffolo, Assistant Professor, University of Padova - Department of Information Engineering, Italy Effects of ESDs on GaN LEDs: a device perspective (Invited)
12:30 PM 30 Mins Dr. Milind Furia, Member of Technical Staff, IP Design, Micron Technology, USA Need for reducing ESD targets for Memory Components (Invited)
1:00 PM 90 Mins Networking Lunch
2:30 PM 30 Mins Dr.-Ing. Andreas Hardock, Sr. Principal Product Application Engineer, Nexperia Germany GmbH, Germany Optimizing Signal Integrity when Using ESD Protection Devices (Invited)
3:00 PM 30 Mins Dr. Sergej Bub, Principal System Level ESD Expert, Nexperia Germany GmbH, Germany High-Speed Interface Design – Balancing Signal Integrity and ESD Robustness. Part 2: Optimizing ESD Robustness (Invited)
3:30 PM 30 Mins Dr. Joost Willemen, Senior Principal, Infineon Technologies, Germany Characterizing TVS Devices for Antenna Protection: ESD Robustness Meets RF Linearity (Invited)
4:00 PM 30 Mins Coffee Break
4:30 PM 10 Mins Mr. M M C Kishore, Founder and CEO, Global Marketing Services Tools for Emerging Technologies in chip fabrication, assembly and characterization (Platform Presentation)
4:40 PM 10 Mins Mr. Thomas Tatry, Application Engineer, SENTECH Instruments, Germany SENTECH Instruments - Experts in Plasma process and thin Film metrology (Platform Presentation)
4:50 PM 10 Mins Mr. Sabarigresan Murugan, Application Scientist, Park Systems India Nanoscale Failure analysis using AFM (Platform Presentation)
5:00 PM 15 Mins Dr. Vasu Duvvury, Professor (Retired), University of North Texas, USA Art and Symbolism of the Hand Fan: Its Global and Historical Importance (Contributed Talk)
5:15 PM 15 Mins Mr. Harshit Dhakad, Intel From simulation to silicon: RF ESD Design and characterization for Wifi tranceiver (Contributed Talk)
5:30 PM 15 Mins Mr. Srinivasamuni Adepu, Senior IO layout Manager, Mixed Singal IP group, ASIC, SanDisk Corporation ESD Protection: Layout Challenges, Verification, and Silicon Learnings (Contributed Talk)
5:45 PM 15 Mins Mr. Prashanth, Staff Engineer - ESD Engineer, Marvell Technology 3D ESD PERC Verification in Advanced Packaging (Contributed Talk)
6:00 PM 15 Mins TBD TBD (Contributed Talk)
6:15 PM 15 Mins TBD TBD (Platform Presentation)
6:30 PM 15 Mins Concluding Remarks & Vote of Thanks & 8th InEW Announcement
6:45 PM 15 Mins Networking, Poster, Hi-tea, and See You @ 8th InEW

* In online mode