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Adaptive Self-Healing ESD Protection for IoT Using AI-Driven Dynamic Voltage Clamping
Mudit Kumar Singh
(Department of Electronic Science, University of Delhi)
Abstract:
This work introduces a novel AI-reconfigurable ESD protection circuit for IoT systems. Combining GaN TVS arrays with tunable MIM capacitors, the design dynamically adapts clamping topology in real-time using embedded machine learning (ML). The ML classifier predicts surge profiles (<100 ns) to optimize protection during oscillating discharges, reducing residual voltage by 40% vs. static solutions. Validated via SPICE and TLP testing, the system achieves 30 kV IEC 61000-4-2 robustness with 50% smaller footprint and 30% lower BOM cost. Applications include wearables, medical sensors, and industrial IoT where size and adaptive reliability are critical.
From Gate to Ground: A Beginner’s View into On-Chip ESD DesignFrom Gate to Ground: A Beginner’s View into On-Chip ESD Design
Nisarga D K
(Tapeout engineer)
Abstract:
Electrostatic Discharge (ESD) is one of the major causes of chip failure in modern VLSI systems. As devices shrink and voltages decrease, even small electrostatic charges can damage sensitive transistors. This poster presents a beginner-level overview of ESD and common on-chip protection techniques such as diode clamps and gate-grounded NMOS (GGNMOS). The aim is to highlight how ESD protection is integrated into the design flow and why it is critical during chip handling, testing, and packaging. Simple block diagrams and real-world examples will be used to explain the concepts clearly. This work is intended for students and new professionals looking to understand the basics of ESD-safe design in semiconductor devices.Electrostatic Discharge (ESD) is one of the major causes of chip failure in modern VLSI systems. As devices shrink and voltages decrease, even small electrostatic charges can damage sensitive transistors. This poster presents a beginner-level overview of ESD and common on-chip protection techniques such as diode clamps and gate-grounded NMOS (GGNMOS). The aim is to highlight how ESD protection is integrated into the design flow and why it is critical during chip handling, testing, and packaging. Simple block diagrams and real-world examples will be used to explain the concepts clearly. This work is intended for students and new professionals looking to understand the basics of ESD-safe design in semiconductor devices.
Structural Innovations for ESD Protection in BSPDN: Backside Ground Sink Layer and Dual-Layer TSV Isolation
P R Teja Sree
(Graduate Student)
Abstract:
As Backside Power Delivery Networks (BSPDN) emerge in advanced 3D IC packaging, new ESD vulnerabilities surface due to high-density TSVs and exposed backside pads. This poster proposes two novel strategies to enhance ESD resilience (1) a Backside Ground Sink Layer (BGSL): a dedicated, low-resistance grounding plane beneath the BSPDN to instantly absorb discharge and redirect current away from logic paths, and (2) Dual-Layer TSV Isolation (DLTI): a reengineered TSV structure with an isolating shell to contain ESD within the core and prevent cross-talk. Together, these techniques offer a scalable, layout-friendly approach for next-generation chip stacking under extreme performance demands.
System-Level ESD Resilience with Verilog and Adaptive Filtering
Ambika
(BMS COLLEGE OF ENGINEERING)
Abstract:
This system-level approach integrates Verilog-A device models with Xilinx Vivado-based fault injection to simulate ESD resilience in digital architectures. It abstracts electrostatic discharge effects into programmable test vectors (IEC 61000-4-2 compliant) while employing adaptive median filtering with dynamic window sizing (3×3 to 5×5) for noise mitigation. The framework enables co-simulation of analog ESD transients (via Spice) and digital signal integrity verification (BRAM/CRC checks), achieving 5× faster validation cycles than physical testing. Validated on medical ECG systems, it reduces phase errors by 98% in 28nm FDSOI nodes. While quasi-static modeling limits full electrothermal analysis, the workflow supports ISO 26262 ASIL-D compliance, making it ideal for automotive/medical ICs requiring <10% signal distortion under 150MHz clock domains.
Compact ESD Protection Strategies for IoT Edge Devices
Srinidhi Shetty
(DSCE,Bangalore)
Abstract:
With the increasing deployment of IoT edge devices in uncontrolled environments, robust yet compact ESD protection becomes critical. GGNMOS and diode-based ESD clamps optimized for low-power and area-constrained applications. Emphasis will be on understanding trade-offs in clamping voltage, leakage current, and layout impact. Simulation-based evaluation methods will be proposed to assess the performance of basic ESD topologies. This work aims to offer a learning-oriented framework for beginners in chip design to understand real-world reliability challenges in ASIC development.
Safeguarding IC Integrity: Runtime-Efficient Detection of ESD Devices Misuse with Calibre PERC
Kunwar Tarun, Kislaya Sharma, Ertugrul Demircan
(NXP India Private Limited, Noida, India)
Abstract:
Unintended deployment of ESD protection devices in non-ESD circuitry introduces critical risks, including elevated leakage currents, timing degradation, absence of aging models, and susceptibility to latch-up. Despite functional correctness, such violations degrade area efficiency, yield, and long-term reliability. This work presents a robust methodology leveraging Calibre PERC to detect misplaced ESD devices at both schematic and layout levels. The approach integrates rule-based checks and hierarchical analysis to optimize runtime and detection accuracy. Early identification enables pre-silicon resolution of ESD misuse, ensuring design robustness and compliance with reliability constraints across advanced process nodes and complex mixed-signal design environments.
Custom ESD Protection for 10V-Compliant Neural Stimulator in 65nm CMOS Technology
Tanay Das, Naef Ahmad, Sandip Lashkare, Laxmeesha Somappa
(IIT Gandhinagar, IIT Bombay)
Abstract:
Implantable neural circuits have broad applications, such as treating neurological disorders. To ensure reliability against electrostatic discharge (ESD) damage during fabrication, packaging, or handling, robust ESD protection is essential. A fully integrated, closed-loop neuromodulation SoC, featuring on-site recording, digital processor, and a high-voltage compliant stimulator, constrained by cost, is implemented in 65 nm CMOS technology. Custom ESD protection is needed, as foundry-provided solutions cannot withstand the high voltages required for reliable current stimulation. This work introduces a ±10V compliant stimulator with integrated custom on-chip ESD protection in a 65 nm process, validated for the HBM model via post-layout TLP simulations.
Asymmetric NIPIN Diode for Low-Voltage, Low-Capacitance Unidirectional ESD Protection
Navin Maheshwari, Krish Patel, Kshitij Agarwal, Hasan Ali, Ritesh Kumar, Sandip Lashkare
(Indian Institute of Technology, Gandhinagar)
Abstract:
Ultra-low‑voltage TVS diode is critical for the protection of low‐voltage electronics such as Sub‑20 nm I/Os, next-gen USB, Thunderbolt etc. Existing system‑level solutions rely on pn diodes operating in Zener breakdown, limited by the bandgap, and even advanced designs - such as punch‑through or graded‑base diodes – the voltage is ~1V. Here, we propose a triangular‑barrier silicon NIPIN diode, achieving breakdown from 0.5V up to 3V utilizing sub-bandgap impact ionization. Further, symmetry control is shown by adjusting intrinsic region lengths and dopings. Compared to existing devices, it offers near‑ideal standoff and clamping voltages - marking a major advancement for low‑voltage electronics.
Predictive TCAD-Based Design of Customized ESD Protection with Low Clamping Voltage for 10V Neurostimulator Circuits in 65nm CMOS Technology
Navin Maheshwari, Laxmeesha Somappa, Sandip Lashkare
(Indian Institute of Technology, Gandhinagar & Indian Institute of Technology, Bombay)
Abstract:
Effective Electrostatic Discharge (ESD) protection is critical for 10V neurostimulator circuits in 65nm CMOS, where strict area and voltage constraints limit design choices. Standard diodes fail to meet breakdown voltage (>10V), clamping voltage (<16V), and dynamic resistance (<6Ω). This work presents a TCAD-based Back-to-Back diode ESD protection design. Doping profiles and junction spacing are optimized to match target breakdown and dynamic resistance while minimizing current crowding. The layout, with n-diode centrally positioned and p-diode surrounding it, ensures balanced current flow and reduced thermal hotspots. The final design achieves clamping &th;16V, 10× lower resistance, and area-efficient robust ESD protection.
Physical insights into ultra-low capacitance transient voltage suppression diode for system level ESD protection
G Y
(Indian Institute of Technology Gandhinagar)
Abstract:
To maintain signal integrity, low capacitance ESD protection is essential for the applications having high-speed data interfaces such as HDMI, USB etc. Typical Zener diodes offer good ESD protection, but increasing their area also increases capacitance. Ultra-low-capacitance TVS (ULC-TVS) diode is one of family TVS diodes which provides lower capacitance than standard TVS diodes. This work provides in‑depth physical insights into how fabrication aspects(geometry, doping profiles, finger structures, trench design) impact ULC‑TVS ESD performance. It also proposes a design strategy that improves ESD protection while keeping low capacitance and reducing area usage compared to conventional Zener diodes.
Physical insights into ultra-low capacitance transient voltage suppression diode for system level ESD protection
G.Yashan Kumar , N. Maheshwari, Sandip Lashkare
(Indian Institute of Technology Gandhinagar)
Abstract:
To maintain signal integrity, low capacitance ESD protection is essential for the applications having high-speed data interfaces such as HDMI, USB etc. Typical Zener diodes offer good ESD protection, but increasing their area also increases capacitance. Ultra-low-capacitance TVS (ULC-TVS) diode is one of family TVS diodes which provides lower capacitance than standard TVS diodes. This work provides in‑depth physical insights into how fabrication aspects(geometry, doping profiles, finger structures, trench design) impact ULC‑TVS ESD performance. It also proposes a design strategy that improves ESD protection while keeping low capacitance and reducing area usage compared to conventional Zener diodes.
ESD Challenges in 2nm & Beyond : Providing Innovative Solution for Next-Gen Memory and Logic Devices
Sunilkumar
(Globalfoundries)
Abstract:
eFUSE technology, widely adopted as a One-Time Programmable (OTP) memory solution, plays a critical role in security-centric applications across various process nodes. Beyond its security applications, eFUSE is instrumental in enabling redundancy, chip self-repair, and reconfiguration—both at the factory and in-field—thereby enhancing overall chip yield[1]. These capabilities are significantly augmented through integration with advanced Built-In Self-Test (BIST) and Built-In Self-Repair (BISR) methodologies[2].
From an implementation standpoint, the long-term reliability of electrical fuses is paramount to ensuring sustained chip functionality. Consequently, robust Electrostatic Discharge (ESD) protection becomes essential in eFUSE design. This poster presents a detailed case study addressing the system-level verification challenges encountered during the development of ESD protection for eFUSE IP in 55BCDlite technology. Key focus areas include technology compatibility, drive strength optimization, and compliance with Human Body Model (HBM) and Charged Device Model (CDM) test requirements. The study also outlines ESD pass/fail criteria at the subsystem level, offering insights into the design and verification strategies necessary for reliable eFUSE deployment in mixed-signal and high-voltage environments.
[1] W. Tonti et al., “Product Specific Sub-Micron E-Fuse Reliability and Design Qualification” IRPS Proceedings, p161 (2004)
[2] https://www.design-reuse.com/article/61534-optimal-otp-for-advanced-node-and-emerging-applications
D&R Industry Articles
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IRC- IO RING COMPILER
Priyanshi Jain, Praveen Jakki, Avinash Gupta, Anurag Mittal
(Synopsys India Pvt. Ltd.)
Abstract:
IO Ring is a key factor for any SoC Design and Building the same manually is a challenging task. Designer also need validate the IO ring for all the ESD Integration rules.The proposed IO Ring Compiler tool establishes the automated IO RING, incorporating necessary cells and adhering integration rules with inbuilt validation. It also validates any pre-built IO ring DEF. The advantages are robust and flawless IO ring development, reduced cycle time and increased Productivity. The proposed utility has been verified across multiple technology nodes and is in use for all IO RING REVIEW queries received through Customers.
IO integration rule to streamline the early PERC signoff at SoC level
Annu Kumari, Avinash Gupta, Anurag Mittal
(Synopsys)
Abstract:
PERC signoff is crucial for reliability checks of ESD/Latch-up to provide the final SoC signoff. SoC architecture has diverse interface IPs, including IOs, which are more prone to ESD/latch-up risk. Nowadays, industries are looking for SoCs which are validated with PERC tools. PERC validation at SoC is complex, since thousands of PERC rules, high run-time, and late catching of PERC violations causing delays in signoff. In this poster, we exhibit PERC analysis done during the IP development such that SoC designers only need to maintain the IO Integration-rule and robust connectivity between Bump to Signal/power/ground pad for early PERC signoff.
ESD CDM Target Management using Optimized I/O
Hemant Ahire, Bhawana Adhikari, Siddharth Singh, Anurag Mittal
(Synopsys India Pvt Ltd)
Abstract:
Most of the foundry provides different ESD diodes, supply clamps depending on CDM target current i.e. 5A, 7A, 10A etc. For lower techno nodes higher CDM current target requires very big ESD components sizes which consumes significant area and leakage budget of a SOC. In this poster we present how we can use same optimized I/O across all CDM targets. We have developed few solutions during I/O ring implementation i.e. by varying distance rules, split clamps etc.
Electrifying Reliability: Fast-Track ESD Validation for Next-Gen Medical & Automotive Chips
AMBIKA
(BMS COLLEGE OF ENGINEERING)
Abstract:
This system-level approach integrates Verilog-A device models with Xilinx Vivado-based fault injection to simulate ESD resilience in digital architectures. It abstracts electrostatic discharge effects into programmable test vectors (IEC 61000-4-2 compliant) while employing adaptive median filtering with dynamic window sizing (3×3 to 5×5) for noise mitigation. The framework enables co-simulation of analog ESD transients (via Spice) and digital signal integrity verification (BRAM/CRC checks), achieving 5× faster validation cycles than physical testing. Validated on medical ECG systems, it reduces phase errors by 98% in 28nm FDSOI nodes. While quasi-static modeling limits full electrothermal analysis, the workflow supports ISO 26262 ASIL-D compliance, making it ideal for automotive/medical ICs requiring <10% signal distortion under 150MHz clock domains.
TCAD modeling of STI diode response to ultrafast ESD event during D2D and D2W bonding process
Emanuele Groppo1,2 , Harshit Dhakad 3, Harald Gossner1, Anand Sharma 3
(1Intel Deutschland GmbH, 2Technische Universität München, 3Intel Technologies Inida Pvt. Ltd)
Abstract:
Charged Device Model (CDM) events can occur during the bonding process in 2.5D or 3D technologies. Simulations and measurements show that such CDM events are characterized by ultrafast rise times (few tens of picoseconds) and peak current pulses that can reach several hundreds of milliamperes. In such conditions, diode forward recovery effect causes voltage overshoots that can lower the failure level of thin gate oxide (GOX) victims. TCAD simulations show that voltage overshoots increase with faster rise time pulses, posing a severe reliability threat for tightly constrained ESD protection of Die-to-Die (D2D) and Die-to-Wafer (D2W) interfaces. To ensure realistic simulation results, a voltage-driven simulation setup is proposed replacing the commonly used current-driven one. Diode transient response becomes the main concern for ESD protection of such interfaces to comply with GOX safe operating limits.
Method of ESD characterization and modeling of ESD networkfor CDM predictive simulation
Nicolas Richaud, Ritesh Agarwal, Harshit Dhakad, Harald Gossner, Florian Klotz, Umair Ishfaq, Robert Haeussler, Krzysztof Domanski, Anand Sharma
(Intel)
Abstract:
This poster presents a methodology for electrostatic discharge (ESD) characterization and modeling of ESD victims experiencing fast voltage overshoots under Charged Device Model (CDM) conditions. Dedicated test structures were developed to accurately characterize overshoot effects using an ultrafast Transmission Line Pulse (UFTLP) setup with current pulse rise times (>20 picoseconds). The diode model was adjusted to reflect forward recovery behavior during the rapid rise times of CDM current. Additionally, a testbench for predictive CDM simulations is proposed, enhancing the reliability of ESD protection strategies by accurately simulating the fast transient responses of ESD victims.
Performance projection of Junction-less CFET
Ayaz Mumtaz Ansari
(Jamia Millia Islamia)
Abstract:
In this work, we present the device-level modeling and comparative performance analysis of a 2D Complementary Field-Effect Transistor (CFET) and its Junctionless counterpart (JL-CFET) using Synopsys Sentaurus TCAD. The electrical behavior of both devices is evaluated through extraction of NMOS and PMOS transfer characteristics, voltage transfer characteristics (VTC), and transient response curves. Furthermore, we investigate the influence of gate metal work function (WF) variation on the performance of both NMOS and PMOS configurations, and identify optimized WF values for the JL-CFET structure to enhance its performance. To complement the TCAD-based study, a predictive machine learning model is developed that estimates the transfer characteristics of JL-CFET devices for a given WF input. The proposed integration of TCAD simulations with AI-based prediction offers a powerful approach for accelerating device optimization in future CMOS technologies.
Self-Contained Lattice-Ag Filament Analog Switching in AgHfO₃₋ₓ Memristors Enabling Stable Synaptic Behavior and Associative Learning
SWARAJ MUKHERJEE
(IIT JODHPUR)
Abstract:
Silver-doped perovskite AgHfO₃₋ₓ naturally generates uniform hybrid conduction paths of lattice Ag and oxygen vacancies, removing the need for external active electrodes and preventing random filament formation typical of HfO₂ devices. Introducing extra oxygen during deposition reduces vacancy density, boosting switching stability and ON/OFF contrast. The Au/AgHfO₃₋ₓ/FTO memristor delivers stable analog resistive switching, emulates key synaptic behaviors—potentiation, depression, paired-pulse facilitation—and supports associative learning via a Pavlovian conditioning protocol. CMOS compatibility and combined memory–neuromorphic performance make AgHfO₃₋ₓ memristors a scalable hardware platform for brain-inspired computing.
CuGa₂O₄ based Memristor device for Synaptic Plasticity and Associative Learning
Ayan Chatterjee
(IIT JODHPUR)
Abstract:
We illustrate a spinel CuGa₂O₄-based memristor showing stable bipolar resistive switching under low voltage operation and with good endurance, which is a prime contender for future memory devices. Besides digital memory, the device exhibits analog behavior allowing synaptic plasticity such as paired-pulse facilitation, potentiation/depression, and conversion from short-term to long-term plasticity. Importantly, it replicates associative learning based on Pavlovian conditioning. These characteristics identify the two-fold potential of CuGa₂O₄ memristors for both neuromorphic and non-volatile memory purposes, making them strong contenders to realize brain-inspired hardware systems.
Formation Mechanism and Spectroscopic Characterization of ZnO Layers Buried in Si/ZnO/HfO₂ Heterostructure
Jay Sharma
(Saha Institute of Nuclear Physics)
Abstract:
Metal oxides are vital for optoelectronic, piezoelectric, and magnetic applications. This study demonstrates the controlled synthesis of zinc oxide (ZnO) thin films on n-type silicon via internal oxidation of a buried zinc (Zn) layer beneath hafnium dioxide (HfO₂). X-ray diffraction confirmed the full conversion of Zn into a ZnO/HfOx heterostructure. Low-temperature photoluminescence at 4 K showed sharp near-band-edge emissions at ~3.37 eV, indicating high optical quality. These findings highlight a viable route to fabricate buried wide-bandgap oxide heterostructures, offering potential for advanced electronic and photonic device integration across a variety of emerging technologies.
DIRECT: Enabling Scalable Processing-In-Memory via DPU-to-DPU Communication
Prateek P Kulkarni
(PES University)
Abstract:
The exponential growth in dataset sizes and model complexity has made distributed training a necessity for modern machine learning (ML) workloads. However, conventional processor-centric architectures struggle with the data movement bottleneck, leading to suboptimal performance and energy efficiency. Processing-In-Memory (PIM) has emerged as a promising solution, but current PIM systems face critical scalability challenges due to mandatory host CPU mediation for inter-DPU communication. We present DIRECT, a novel architecture enabling CPU-free DPU-to-DPU communication through a hierarchical crossbar network with hardware-level synchronization primitives. Our key innovations include: (1) Atomic Gradient Accumulation Units (AGAUs) for efficient local parameter updates, (2) a Distributed Synchronization Controller (DSC) for global coordination, and (3) locality-aware training algorithms. Comprehensive evaluations on industry-standard ML workloads demonstrate a 2.9× speedup in training time, 65% reduction in energy consumption, and 92% parallel efficiency at 2048 DPUs (vs. 25% baseline), all with minimal hardware overhead (0.51mm² area, 205mW power in 28nm process). DIRECT outperforms state-of-the-art PIM systems and bridges the gap with specialized GPU accelerators for distributed ML training, paving the way for more energy-efficient and scalable ML infrastructures.
Enhanced ESD Reliability of AlGaN/GaN MIS-HEMTs Using a p-Type Oxide Passivation
Mohammad Ateeb Munshi
(Indian Institute of Science)
Abstract:
This work presents a novel device-level solution to enhance ESD reliability of AlGaN/GaN MIS-HEMTs using a p-type AlTiO-based passivation. Extensive ESD testing, including TLP and VF-TLP under various stress conditions, shows that AlTiO significantly outperforms conventional SiN passivation. It suppresses channel electric field peaks, reducing self-heating and eliminating thermoelastic strain, thus improving off-state and semi-on-state ESD performance. Enhanced robustness is also observed under floating gate and gate–source stress. Raman, thermoreflectance, EL, and FE-SEM analyses reveal reduced thermal and impact ionization failures, validating AlTiO's effectiveness in improving ESD resilience and uncovering associated failure mechanisms.
TCAD Calibration Methodology for Accurate ESD Simulation
Mitesh Goyal, Mahesh Vaidya, Mukesh Chaturvedi, Mayank Shrivastava
(Indian Institute of Science)
Abstract:
For accurate ESD simulation device architecture and its operational physics impacts the overall behavior of the device. This demands good calibration of the TCAD environment with the physical process. The triggering mechanism of most of the ESD protection device is driven by an avalanche breakdown event, which triggers in the critical electric field within the device. The field distribution has a major dependency on the doping profile of the device. And therefore, it is highly recommended to have a calibrated doping profile in TCAD simulations.
In this poster, we are presenting how to simulate the ESD devices (for example: SCR) with a calibrated TCAD environment. The calibration starts with obtaining the actual doping profiles for the TCAD simulation, where we use PDK (Process Design Kit) data as an input. In order to capture the N+/P+ profile; we use the same cross-section of diffusion resistor as the PDK layout with various lengths. The different values of the diffusion resistor's IV-characteristics have been extracted with a circuit simulator and can be used as an input to TCAD. While simulating the diffusion resistor in TCAD the related physics has been invoked, which helps the TCAD to capture all the important physics in order to replicate the accurate IV-behavior. The matching of TCAD and PDK simulated characteristics of diffusion resistors has provided us with the doping profile for N+/P+ taping. The same procedure has been followed with the N-Well and P-Well resistor in order to get the N-Well/P-Well doping profile. This calibrated N+/P+ doping profile along with N/P-Well doping profile has been further used to create P+/N-Well Diode and N+/P-Well diode for further validation. Furthermore, all these calibrated profiles have been used in order to calibrate MOSFET in order to capture a little more information about the device gates. The MOS-Capacitance and MOSFET IV characteristic from the PDK has been used in TCAD to extract more information like; Vt Implant profile, Halo Implant profile, oxide thickness and so on.
The calibrated doping profiles extracted through TCAD simulations, are then used to create the digital twin of SCR. As in the ESD simulation, where the high voltage and high current injection event happens, requires a very precise calibration environment in terms of physics declaration also. The charge transport models like Doping, Electric Field and Temperature dependent models have been invoked during the simulation. Moreover, to capture the device temperature role ESD simulation accurate thermal boundary condition has been used along with the thermal resistance component. This is very essential to capture the instability which occurs when a device triggers from off-state to on-state.
By following this procedure and techniques, we were able to perfectly match the ESD parameters like Trigger Voltage, Trigger Current, Holding Voltage, Holding Current, Failure Current, etc. Along with this, the real-time transient oscillations have also been captured during the transition of the device from trigger to holding point, which happens due to the moving filament event.
Comparative study for optimum placement of substrate trigger points in STI bound SCR
Mukesh Chaturvedi
(Samsung Semiconductor India Research )
Abstract:
To bring down the trigger voltage (Vt1) of a STI bound SCR within ESD design window, we need to inject charges into the substrates to enable the high base current needed for early turn on of the parasitic PNP or NPN transistors. The placement of this injection point is closely related to the effect of injected charges on trigger voltage (Vt1), Holding voltage (Vh) and Triggering time. Hence position of trigger point is strategic in design of SCR. We present comparative study of various locations of trigger points in this poster.
Improving the latch up robustness of SCR by Injection terminal engineering
Jigyasa Shrivastava
(Indian Institute of Science)
Abstract:
Substrate Triggering is one of the most popular method to bring the trigger voltage of SCR in ESD safe window of operation. But the placement of this current injection point for SCR trigger impacts its latchup susceptibility. In this poster, an state of the art STI bounded SCR with trigger circuit is implemented in a bulk planar technology and many variations of current injection point is implemented to test the latch up robustness of the devices. We observe that though ESD characteristics are better for certain geometrical variations, but they come at the cost of lower latch-up robustness.
Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR
Mitesh Goyal Mukesh Chaturvedi Mahesh Vaidya Mayank Shrivastava
(Indian Institute of Science)
Abstract:
In this work co-optimization of silicon-controlled
rectifier (SCR) ESD characteristics with its low voltage trigger
circuit is presented. Resistance and Capacitance (RC) controlled
thick gate NMOS and PMOS based circuits have been explored
and compared. The design approach is discussed and presented
for low trigger SCR for two different trigger circuits. In the
process we find that some of the trigger circuits previously
reported in literature do not work as desired until co-optimized
device engineering techniques are used. The circuit insights are
explored using well calibrated electrothermal 3D process and
device TCAD mixed mode simulations.
Small Signal Assisted Monitoring of Channel in TMD FETs
Utpreksh Patbhaje
(Indian Institute of Science)
Abstract:
We propose a small signal analysis methodology which is capable of monitoring TMD channel health in FETs and can be used to evaluate WF changes in TMD devices providing a quick way to assess stress history of the TMD channel. The evolution of small signal impedances of pristine device till breakdown under ON, OFF, and Open gate conditions are analyzed using C-f and C-V sweeps. Incremental stressing field across source-drain reveals a metallic nature of channel encountered well before catastrophic breakdown. This methodology can be used to define safe operational regimes for the TMD FETs.
Inconsistencies in current Trends in MoSe2 FETs Under Long Term Operation
Megha Yadav
(Indian Institute of Science)
Abstract:
TMDs like MoSe₂ are promising materials for future electronics, but realizing both NMOS and PMOS functionality remains challenging. This study investigates the conduction behavior of Pd-contacted MoSe₂ FETs under back-gated vacuum operation. After applying lateral fields, we observed enhanced n-type and degraded p-type currents, linked to strain-induced effects. The results show a 25% increase in n-type and 300% decrease in p-type conduction. Strain, arising even under low fields, impacts ambipolar devices due to inverse piezoelectric effects. This emphasizes that in order to guarantee stable n- and p-type operation, strain-induced inverse piezoelectric effects must be addressed in future 2D device frameworks.
Charge Neutrality Point Alignment Strategy using Terminal Voltages in MoSe2- FETs
Raising Archana Bairiganjan Mohapatra
(Indian Institute of Science)
Abstract:
2D materials like MoSe₂ hold promise for next-generation electronics due to features such as ambipolarity and tunable charge neutrality. However, intrinsic n-type behavior and Fermi-level pinning at contacts limit their effectiveness in sensing applications. We present a charge neutrality point (CNP) alignment strategy using terminal voltages in MoSe₂ FETs, where Pd-contacted back-gated devices exhibit tunable ambipolarity. By keeping a constant VSD = 1 V/μm and varying drain offset (−15 V to +30 V), we shift the threshold voltage from −12 V to +18 V and control VCNP. This electrostatic modulation enables resistance tuning from 21 MΩ to 0.24 MΩ. Such deterministic control over the CNP is pivotal for applications in photodetectors, chemical sensors, and analog amplifiers, where accurate modulation of current around the threshold voltage is essential for optimal performance