Platform Presentations
Mr. Sadaf Arif Siddiqui
GM-Industry Marketing
Keysight Technologies
Talk Title:
Advancements in Semicon test validation with ESD perspective
Abstract:
With multiple advancements in the field of Semicon design and manufacturing and with high speed, cutting edge requirements ESD plays a critical role.The talk will highlight some of the latest test methodologies and solutions to handle these complicacies.
Bio:
Sadaf A Siddiqui is working as Marketing head for automotive, academia & aerospace-defense segment and associated technologies with Keysight Technologies India. He works very closely with research institutes (government & academia) as well as manufacturing organizations working in some of the cutting-edge technologies and application areas. He has got more than 22 years of work experience in Test & Measurement, embedded and software industry domain. Prior to this role, Sadaf has worked in different roles like Technical Application Engineer, Global Program Manager focusing on high speed digital, wireless communication and quantum. He has been active voice of customer working closely with design & validation team for solutions enhancements. Sadaf has delivered various talks in industry forums and panel discussions. He is an active contributor in Keysight technical case studies program and Electronics and Telecom media for technology and T&M articles
Mr. Gopikrishna Siddula
Senior Manager, Mixed Signal IP-IO Design
Western Digital
Talk Title:
Designing ESD-Robust ASICs: A Practical Approach for Teams Without ESD Specialists
Abstract:
Ensuring ESD robustness in ASICs without an internal ESD expert team demands disciplined design practices and smart use of foundry resources. This presentation outlines practical guidelines for IP and top-level design, focusing on clamp strategies, I/O protection, and cross-domain handling. Key layout techniques such as guard rings and optimized current paths are discussed. EDA-based verification and foundry rule checks are emphasized to meet industry ESD standards and achieve first-pass silicon success
Bio:
Gopikrishna Siddula has been part of the Mixed-Signal IP team at Sandisk for the past 12 years, specializing in the development of high-performance memory interface I/Os across various Sandisk product lines. He holds an M.S. from IIIT Hyderabad. His areas of expertise include analog-mixed signal design and high-speed interface I/O design and integration.He is an inventor on four granted USPTO patents, two filed patents, and one trade secret, covering innovations in I/O design, ESD protection, and memory interface technologies. Outside of work, he enjoys movies, traveling, and photography.
Prof. Laxmeesha Somappa
IIT Bombay
Talk Title:
On the ESD requirements and implementation challenges of Neural SoCs
Abstract:
Modern Closed-loop Neuromodulation devices help alleviate disease symptoms like epilepsy and Parkinson's tremor using intelligent brain stimulations [1]. Other kinds of neural processors, like phase synchrony processors, rely on deep brain stimulation (DBS) with on-chip rapid phase feature extractions to provide a therapeutic solution for various neurological and psychiatric disorders [2]. With the advent of such devices, the security of the devices becomes an important aspect and is hence associated with power-efficient crypto security engines [3,4]. Such devices are realized as system-onchips (SoCs) with high-density neural (ECoG/AP band) recording analog front-end (AFE), digital backend processors/classifiers [5,6], crypto accelerators and high-voltage compliant programmable neural stimulators. Typically, foundry-provided ESDs are used for the AFE voltage domain (1 V), the digital back-end (<0.7 V) and other associated power management blocks. However, the neural stimulators on the SoC rely on > 10V on-demand generated HV voltage domain in a 65nm CMOS process. This necessitates the need to custom ESD circuits that are implemented in a 65 nm CMOS process to operate beyond 10 V in an on-demand power domain [7,8]. This talk will briefly discuss the challenges associated with the design and implementation of such neural SoCs focusing on ESD design.
- 1. U. Shin, L. Somappa et al., "A 256-Channel 0.227µJ/class Versatile Brain Activity Classification and ClosedLoop Neuromodulation SoC with 0.004mm2-1.51 µW/channel Fast-Settling Highly Multiplexed Mixed-Signal Front-End," 2022 IEEE International Solid-State Circuits Conference (ISSCC)
- 2. U. Shin, C. Ding, L. Somappa, V. Woods, A. S. Widge and M. Shoaran, "A 16-Channel 60µW Neural Synchrony Processor for Multi-Mode Phase-Locked Neurostimulation," 2022 IEEE Custom Integrated Circuits Conference (CICC)
- 3. E. Sarkar, H. Sahu, K. Shaikh and L. Somappa, "On the Implementation of Data Security for Neurostimulation Devices," 2023 IEEE International Symposium on Circuits and Systems (ISCAS)
- 4. A. Garg, T. Amritkar, S. Vijayakumaran and L. Somappa, "A Cryptographic Security Engine With Sequence Tracker for Implantable Neural Stimulation Devices," 2024 IEEE Biomedical Circuits and Systems Conference (BioCAS)
- 5. A. P. Sharma, K. A. Rao and L. Somappa, "Hardware Optimization and Implementation of a 16-Channel Neural Tree Classifier for On-Chip Closed-Loop Neuromodulation," in IEEE Transactions on Biomedical Circuits and Systems, vol. 19, no. 2, pp. 244-256, April 2025
- 6. L. Iyer, A. Bal and L. Somappa, "Calibration-Enhanced 16-Channel On-Chip Seizure Classifier using Gated Recurrent Network," 2025 IEEE International Symposium on Circuits and Systems (ISCAS)
- 7. T. Das, N. Ahmad, L. Somappa and S. Lashkare, "Enhanced ESD Protection Techniques for 10V Neurostimulator Circuits in 65nm CMOS Technology," 2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 2025
- 8. N. Ahmad, S. Lashkare and L. Somappa, "On the ESD Protection for 10V-Compliant Neural Stimulator in 65nm CMOS Technology," 2025 IEEE International Symposium on Circuits and Systems (ISCAS)
Bio:
https://www.ee.iitb.ac.in/web/people/laxmeesha-somappa/
Prof. Sandip Lashkare
IIT Gandhinagar
Talk Title:
Design Challenges and Considerations for Low Voltage System Level ESD Protection Devices
Abstract:
Low-voltage (sub-1V) electrostatic discharge (ESD) protection devices are critical for safeguarding low-voltage electronics, including low-voltage GPIO for microcontroller units (MCUs), sub-20nm I/Os, and next-generation interfaces such as USB 3.2 Gen2 and Thunderbolt 4. This talk will provide overview of the low voltage system level ESD protection devices available in the market and discuss the challenges associated in enabling low breakdown voltages for typical Zener/Avalanche diodes. Further, the discussion will cover different physical mechanisms such as punch through, sub-bandgap impact ionization which can be utilized to overcome the low voltage breakdown limitations and design of ESD protection devices using these mechanisms.
Bio:
Sandip Lashkare is an assistant professor at IIT Gandhinagar. He previously worked as a Senior Research Scientist and Group Leader at the MeLoDe Lab at IIT Bombay. Prior to that, he worked as a Postdoctoral Researcher at Helmholtz-Zentrum Berlin on the development of Ferroelectric Memories, as an ESD Design Engineer at Texas Instruments, and ASIC Engineer at LSI and SilabTech Pvt Ltd. He received PhD in 2020 with “The Naik and Rastogi Award for excellence in PhD research”, and received Intel Ph.D. Fellowship, and Visvesvaraya Fellowship during his Ph.D. in Electrical Engineering at IIT Bombay. He holds an M.Tech from IIT Bombay (2013) and a B.Tech from SGGSIE&T, Nanded (2011). His research focuses on ESD protection technologies and emerging non-volatile memory devices for advanced computing applications.
Mr. Harshit Dhakad
Principal Engineer
Intel Technologies India Pvt. Ltd.
Talk Title:
Unraveling ESD HBM Failure on a Failsafe Interface in an Advanced FINFET Technology Node
Abstract:
This talk provides insights into an HBM failure observed in a product, fabricated using an advance FINFET process node. The failure was detected near the tape-out milestone of the subsequent product stepping. An in-depth analysis of the failure and explores the debugging of the failure through traditional methods, such as Transmission Line Pulse (TLP) measurements is described. A non-conventional approach to modeling of ESD protection, victims to simulate the failure is outlined and the journey towards identifying a viable solution to the ESD failure within the tape-out timeline after considering various trade-offs is described.
Bio:
Harshit Dhakad is Principal Engineer, Electrostatic Discharge and Latch up protection design at Intel Technologies India Pvt. Ltd, with combined experience of 20 years at Intel PESG and former iCDG/Infineon Wireless. Harshit received the B.E. degree with honours in Electronics and Telecommunication Engineering from Ujjain Engineering College Ujjain, India, in 2003. He received the Masters in Technology (M. Tech.) degree at the Indian Institute of Technology, Delhi, India in Integrated Electronics and Circuits in 2005.He leads ESD development, product support and enablement encompassing diverse range of foundry technologies including advance GAA, FINFET and planar CMOS. Harshit specializes in developing and implementing area, capacitance and leakage efficient ESD architecture and custom ESD solutions for RF, mm-wave and HS serial interfaces, and ESD verification of complex SoC’s. These cutting edge ESD solutions are utilized by several Intel and Mobileye products. He is member of executive committee of India ESD Workshop and has filed 12 patents and authored several technical papers on ESD.
Mr. Marcos Hernandez
Senior Staff Scientist
Thermo Fisher Scientific, USA
Talk Title:
Charge Device Model (CDM) Electrostatic Discharge Test Using Low Impedance Contact CDM Method (LI-CCDM)
Abstract:
ESD stress in the form of Charge Device Model (CDM) can be challenging for very small devices such as semiconductor dies. The typical Field Induced CDM (FI-CDM) is and air discharge ESD affected by environmental conditions having a profound effect on waveform repeatability, particularly humidity. New methods for testing CDM susceptibility are considered that involved having electrical contact with the pin under test. One of the contact methods considered is Low Impedance Contact CDM or LI-CCDM. This technical talk is a review of how LI-CCDM works, how the data is acquired and what calculations are involved in calculating the peak current. It presents the technical advantages of using LI-CCDM as compared to FI-CDM under certain test conditions.
Bio:
Marcos Hernandez is the Senior Manager of R&D for the ESD line of products at Thermo Scientific in Tewksbury, MA. Thermo Scientific produces ESD test equipment for HBM, MM, CDM, TLP and Latch Up verification. A former member of the JEDEC JESD 14.1 Working group, and current member of the ESDA HBM/JEDEC joint working group, CDM and MM, before his position at Thermo Scientific he has worked at Oryx Instruments as senior systems engineer, PRI Automation as an engineering consultant and at Process Diagnostics in Sunnyvale CA as the Senior Systems Engineer for the production of Ion implanter optical monitors. He holds multiple patents in the area of ESD and measurement, including a patent for a mercury substitute in relays. Marcos was a full time electronics and Semiconductor Manufacturing professor at San Jose City College for nine years and received a BS degree in Chemical Engineering from the University of Guanajuato, Mexico.
Mr. Yaddanapudi Vamsi Krishna
Director ACE, Electronics
Ansys Software Pvt. Ltd.
Talk Title:
Simulation Solutions for Electrostatic Discharge
Abstract:
In this talk, I will cover challenges that arise from ESD events in Electronics products design and development. I will also cover on how simulation tools can help in design and understanding failures due to ESD events along with use cases.
Bio:
Vamsi Krishna has more than 19 years of experience in engineering simulation across Electronics, HVAC and semiconductor industries. Vamsi is in Hyderabad@India. In his current role, Vamsi leads the Ansys India-ASEAN Electronics technical organization and engages with Ansys customers for devising and deploying model-based engineering practices aimed at supporting their digital transformation and “shift-left” journey in product development. Vamsi has significant experience in Chip Package System methodologies and process flow automation. Vamsi hold 4 patents and 1 trade secret in Electronics area and has papers and publications in several reputed conferences and journals. Vamsi has completed his Master’s degree from Indian Institute of Technology, Kanpur.
Mr. Tristen Tan
Regional Business Development Manager – Oscilloscopes, ASP Region
Rohde & Schwarz
Talk Title:
ESD Transient Pulse Verification Based on Oscilloscope
Abstract:
This presentation outlines the methodology for verifying Electrostatic Discharge (ESD) transient pulses using oscilloscopes, in accordance with standards. It highlights the importance of high-bandwidth instruments, accurate rise time measurement, and standardized test setups involving ESD simulators and attenuators.
Bio:
Tristen Tan brings over two decades of expertise in the Test and Measurement industry, with a strong focus on oscilloscopes and signal analysis. Currently serving as the Regional Business Development Manager for Oscilloscopes at Rohde & Schwarz, he leads product strategy and business development across the Asia South Pacific (ASP) region. His role involves driving customer engagement, market expansion, and technical enablement for high-performance oscilloscope solutions. Tristen began his career as a Senior ICR Sales Engineer at RSAUS, where he developed deep technical knowledge in High-Speed Serial Interfaces, Power Integrity, and Vector Signal Analysis in the time domain. Over the years, he has held key roles at leading Scientific and Test & Measurement companies, contributing to his broad industry perspective and technical depth. He is a frequent speaker at technical seminars and workshops, sharing insights on signal integrity, compliance testing, and advanced debugging techniques for modern digital designs.
Mr. Surya Viswanathan
ESD engineer
Infineon Technologies AG, Germany
Talk Title:
CDM robustness improvement through decoupling capacitors in advanced CMOS technologies
Abstract:
In this presentation, decoupling capacitors as a method of improving the CDM robustness in a 22nm CMOS technology are shown and a quantitative correlation between the capacitance value used and the resulting CDM pass level is derived. vfTLP was used to investigate the physics behind the observed increase in CDM performance which is extendable to other advanced CMOS nodes.
Bio:
Surya Viswanathan received his Master’s degree in Microelectronics from the Nanyang Technological University (NTU), Singapore in 2017. He is currently an ESD engineer at Infineon Technologies AG, Munich, Germany. At Infineon, he works on ESD topics with focus on characterization, modeling and product support.
Dr. Shin-ichi Iida
Analytical Solutions Lab Manager
ULVAC-PHI
Talk Title:
Advanced Surface and Interface Characterization for Semiconductor Devices Using XPS and SIMS
Abstract:
X-ray Photoelectron Spectroscopy (XPS) and Secondary Ion Mass Spectrometry (SIMS) are powerful tools for analyzing the composition, chemical states, and depth profiles of semiconductor materials. This presentation highlights practical applications of XPS and SIMS in semiconductor
Bio:
Mr. Vinod Kumar
Sr. Design Engineering Architect
Cadence Design Systems
Talk Title:
ESD challenges of Designing high-speed interfaces in advanced nodes
Abstract:
The advancement systems necessitates high-speed interfaces that require innovative Electrostatic Discharge (ESD) protection schemes. These ESD structures need to be optimized to ensure the fine balancing between required protection and performance of high-speed interface. In this talk the presenter will cover the ESD related challenges for high-speed interface designs in advanced technology nodes.
Bio:
Vinod Kumar holds an M. Tech. in solid state technology from IIT Kharagpur and has over 21 years of CMOS industry experience, having worked at Semiconductor Complex Limited, STMicroelectronics, and currently at Cadence Design Systems, with expertise in high-speed memory interface design, PLL & clocking circuit design, Regulator design, CMOS reliability, and analog/mixed signal circuit design, holding 43 U.S. patents and authoring 24 technical papers in various IEEE and technical conferences. He has received multiple awards for his contributions which includes Best Patent Award, Best Paper Award, Corporate Star Silver Award, Cadence Trailblazer Innovation award, Cadence Master Innovation Milestone award and many more.
Ms. Yogendri Vishwakarma
Rambus
Talk Title:
Advanced EOS protection techniques
Abstract:
Electrical over stress(EOS) is an event which can occur when voltage/current exceeds over the maximum rating of the device for a longer duration of time(ms to s). ESD devices can only handle spikes in voltage/current which occur for a shorter duration of time(in ns or less than us). To address the EOS issue, we need to incorporate regulation loops inside the chip which can protect the I/O and CORE devices while also providing the low resistance clamp paths for the current surges which can happen during the EOS stress condition. In this talk, we address the basic implementation details of EOS and also the challenges associated with it.
Bio:
I have done B.Tech from SRMSCET Bareilly (2009-2012) and M.tech from NIT Kurukshetra (2014-2016). Before joining Rambus I was associated with Onsemi(2016 to 2023) where I worked on USB2 redirver and eUSB repeater. I joined Rambus in 2023 where I'm working on analog blocks of DDR5 Server DIMM chipsets - RCD and DDR5 Client DIMM chipsets - CKD.
Ms. Roopa Hegde
Software Applications Technical Lead Engineer
Semiverse Solutions
Talk Title:
Process window optimization for gate-all-around Electrostatic Discharge (ESD) diode
Abstract:
The performance of gated electrostatic discharge (ESD) diode in gate-all-around (GAA) technology is highly sensitive to geometric parameters such as nanowire (NW) cross-sectional area, gate length, and metal contact area. The NW cross-sectional area and gate length are influenced by fabrication process parameters including lithography bias, Si/SiGe etch selectivity, and silicon lateral etch. Additionally, lithography bias and mask misalignment affect the metal contact area. To assess the impact of process variability on ESD diode’s architecture, we simulate the gated ESD diode fabrication process. The process window for an acceptable range of geometric parameters was generated by conducting multiple virtual fabrication runs. This study provides insights into the sensitivity of ESD diode’s geometry to process variations. SEMulator3D®'s advanced process simulation capabilities enable effective optimization of the process window. This virtual fabrication approach accelerates design iterations, reduces reliance on costly physical prototyping, and enhances reliability by accounting for real-world process variability
Bio:
PhD, Nanotechnology, Andhra University. 5 years in industry and 4 years in academia
